1. Field of the Invention
This invention relates generally to circuits used for scan testing of integrated circuits, and relates more particularly to a circuit that generates a self-resetting bypass control.
2. Description of the Relevant Art
In scan testing integrated circuits, it is customary to scan in a test stimulus, initiate a test sequence, and then scan out the result of the test for analysis. The scanning of test data into and out of the chip is controlled by a "test enable" signal applied by the tester to a test enable pin of the chip. The test enable signal goes active (logic high) for one or several clock cycles to shift the test stimulus into the chip, then goes inactive (logic low) for one clock cycle to initiate the test, and then returns to active to shift the test response out of the chip to the tester. During normal use of the chip, the test enable signal is inactive.
In such scan testing, it is common to supply an externally-generated test clock signal to the chip and to isolate internally-generated clock signals. To do so, a "clock bypass" signal is supplied to the chip to control multiplexers to select between the internal clock and the external test clock. The clock bypass signal may also be used to isolate other control signals such as internally-generated set/reset signals. The clock bypass signal is inactive during normal use of the chip.
One disadvantage of the above-described test control signals is that it requires two pins of the chip to be dedicated to test enable and clock bypass functions.